An Infamous Transistor Dilemma: Gate First or Gate Last?

Comments · 167

• JO

  @JohnnyWednesday · 2 years ago

  I struggle with this every morning - too often I'm trapped in the garden, unable to travel to work.

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• SK

  @skylerbowerbank5847 · 2 years ago

  &quot;Patrion, first access, blah blah, you know the pitch&quot;<br>Glad to see the creators are getting tired of the same line every time also 🤣🤣🤣

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• PR

  @prognosticii · 2 years ago (edited)

  Every middle-class American must encounter this debilitating dilemma anytime they trek past their white-picket fence gate, thinking &quot;dammit, it did it again.&quot;

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• WO

  @woohyunkang6965 · 2 years ago

  &quot;Such an amazing lead, so quickly squandered.&quot;

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• CY

  @cypher50 · 2 years ago

  Man, that ending had the same vibe that documentaries about GM&apos;s downfall in the Malaise era have.

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• SA

  @SasquatchsCousin33 · 2 years ago

  Coming off of Intel&apos;s Q2 results, this hits hard

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• EB

  @ebx100 · 2 years ago

  From Swiss watches to atomic layer IC processes... never boring here.

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• AR

  @ArchAngel1508 · 2 years ago (edited)

  @Asianometry your labeling of NMOS and PMOS at <a href="https://www.youtube.com/watch?v=c1MdNHJltNc&amp;t=355">5:55</a> is backwards. The labeling of MOSFET types is done by the doping type of the source and drain, not the body. So an NMOS sits in a PWELL and has n-type doped source and drain, while a PMOS sits in an NWELL with p-type doped source and drain. (Though you are correct in stating that the formal definition of MOSFET type is based on the carrier type when the inversion channel is formed. But its much easier to tell for MOSFETs by looking at the doping in the source and drain. The issue would be compounded if we were looking at enhancement mode vs depletion mode, or the other exotic MOSFET types, but most of the time when people say MOSFETs, they&apos;re referring to enhancement mode.)

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• AD

  @AdvantestInc · 2 years ago

  The detailed exploration of transistor scaling challenges is impressive. It&apos;s clear you&apos;ve put a lot of effort into making these concepts understandable.

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• AA

  @AaronALAI · 2 years ago

  Now Intel is laying off 10k workers and have a untold number of failing cpus 😔☠️

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• LI

  @lightningllama · 2 years ago

  (note to self)<br><a href="https://www.youtube.com/watch?v=c1MdNHJltNc&amp;t=164">2:44</a> -&gt; reason why we use polysilicon instead of aluminium as a gate. and why poly gates make the process self aligning.

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• KY

  @Kyzyl_Tuva · 2 years ago

  We were working on Si-Ge at MIT in the early 1980’s.

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